shithub: riscv

ref: c7d9da8f5a41b833946027c802e0e8d7dd014b22
dir: /sys/src/libc/arm64/cycles.s/

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#define	SYSREG(op0,op1,Cn,Cm,op2)	SPR(((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5))
#define PMCCNTR_EL0			SYSREG(3,3,9,13,0)

TEXT cycles(SB), 1, $-4
	MRS	PMCCNTR_EL0, R1
	MOV	R1, (R0)
	RETURN