shithub: riscv

ref: 7a503757b1251c2746df7bdcd891814c1518cc28
dir: /sys/src/libc/arm64/getfcr.s/

View raw version 
#define	SYSARG5(op0,op1,Cn,Cm,op2)	((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5)

#define	FPCR		SPR(SYSARG5(3,3,4,4,0))
#define	FPSR		SPR(SYSARG5(3,3,4,4,1))

TEXT	setfcr(SB), 1, $-4
	MSR	R0, FPCR
	RETURN

TEXT	getfcr(SB), 1, $-4
	MRS	FPCR, R0
	RETURN

TEXT	getfsr(SB), 1, $-4
	MRS	FPSR, R0
	RETURN

TEXT	setfsr(SB), 1, $-4
	MSR	R0, FPSR
	RETURN