shithub: riscv

ref: 54c94a93f0c9de18f05441eb6ee46d813843c396
dir: /sys/src/libc/arm64/cycles.s/

View raw version 
#define	SYSREG(op0,op1,Cn,Cm,op2)	SPR(((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5))
#define CNTVCT_EL0			SYSREG(3,3,14,0,2)

TEXT cycles(SB), 1, $-4
	MRS	CNTVCT_EL0, R1
	MOV	R1, (R0)
	RETURN