ref: a691c9111a69257e206ce895d35396d0f6225929
dir: /mem.h/
/* * Memory and machine-specific definitions. Used in C and assembler. */ #define KiB 1024u /* Kibi 0x0000000000000400 */ #define MiB 1048576u /* Mebi 0x0000000000100000 */ #define GiB 1073741824u /* Gibi 000000000040000000 */ /* * Sizes: * L0 L1 L2 L3 * 4K 2M 1G 512G * 16K 32M 64G 128T * 64K 512M 4T - */ #define PGSHIFT 12 /* log(BY2PG) */ #define BY2PG (1ULL<<PGSHIFT) /* bytes per page */ #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1)) #define PGROUND(s) ROUND(s, BY2PG) /* effective virtual address space */ #define EVASHIFT 42 #define EVAMASK ((1ULL<<EVASHIFT)-1) #define PTSHIFT (PGSHIFT-3) #define PTLEVELS (((EVASHIFT-PGSHIFT)+PTSHIFT-1)/PTSHIFT) #define PTLX(v, l) ((((v) & EVAMASK) >> (PGSHIFT + (l)*PTSHIFT)) & ((1 << PTSHIFT)-1)) #define PGLSZ(l) (1ULL << (PGSHIFT + (l)*PTSHIFT)) #define PTL1X(v, l) (L1TABLEX(v, l) | PTLX(v, l)) #define L1TABLEX(v, l) (L1TABLE(v, l) << PTSHIFT) #define L1TABLES ((-KSEG0+PGLSZ(2)-1)/PGLSZ(2)) #define L1TABLE(v, l) (L1TABLES - ((PTLX(v, 2) % L1TABLES) >> (((l)-1)*PTSHIFT)) + (l)-1) #define L1TOPSIZE (1ULL << (EVASHIFT - PTLEVELS*PTSHIFT)) #define MAXMACH 16 /* max # cpus system can run */ #define MACHSIZE (8*KiB) #define KSTACK (8*KiB) #define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */ #define TRAPFRAMESIZE (38*8) #define DTBADDR 0x40000000 /* * Address spaces. Kernel, sorted by address. */ #define KZERO (0xffffffff80000000ull) #define KTZERO (KZERO+1*MiB) #define MACHADDR(n) (KTZERO-((n)+1)*MACHSIZE) #define UZERO 0ULL /* user segment */ #define UTZERO (UZERO+0x10000) /* user text start */ #define USTKTOP ((EVAMASK>>1)-0xFFFF) /* user segment end +1 */ #define USTKSIZE (16*1024*1024) /* user stack size */ #define BLOCKALIGN 64 /* only used in allocb.c */ /* * Sizes */ #define BI2BY 8 /* bits per byte */ #define BY2SE 4 #define BY2WD 8 #define BY2V 8 /* only used in xalloc.c */ #define PTEMAPMEM (1024*1024) #define PTEPERTAB (PTEMAPMEM/BY2PG) #define SEGMAPSIZE 8192 #define SSEGMAPSIZE 16 #define PPN(x) ((x)&~(BY2PG-1)) #define SHARE_NONE 0 #define SHARE_OUTER 2 #define SHARE_INNER 3 #define CACHE_UC 0 #define CACHE_WB 1 #define CACHE_WT 2 #define CACHE_WB_NA 3 #define MA_MEM_WB 0 #define MA_MEM_WT 1 #define MA_MEM_UC 2 #define MA_DEV_nGnRnE 3 #define MA_DEV_nGnRE 4 #define MA_DEV_nGRE 5 #define MA_DEV_GRE 6 #define PTEVALID 1 #define PTEBLOCK 0 #define PTETABLE 2 #define PTEPAGE 2 #define PTEMA(x) ((x)<<2) #define PTEAP(x) ((x)<<6) #define PTESH(x) ((x)<<8) #define PTEAF (1<<10) #define PTENG (1<<11) #define PTEPXN (1ULL<<53) #define PTEUXN (1ULL<<54) #define PTEKERNEL PTEAP(0) #define PTEUSER PTEAP(1) #define PTEWRITE PTEAP(0) #define PTERONLY PTEAP(2) #define PTENOEXEC (PTEPXN|PTEUXN) #define PTECACHED PTEMA(MA_MEM_WB) #define PTEWT PTEMA(MA_MEM_WT) #define PTEUNCACHED PTEMA(MA_MEM_UC) #define PTEDEVICE PTEMA(MA_DEV_nGnRE) /* * Physical machine information from here on. * PHYS addresses as seen from the power64 cpu. * BUS addresses as seen from peripherals */ #define PHYSDRAM 0 #define MIN(a, b) ((a) < (b)? (a): (b)) #define MAX(a, b) ((a) > (b)? (a): (b)) #define BIT(i) (1<<(31-(i))) /* Silly backwards register bit numbering scheme */ #define SBIT(n) ((ushort)1<<(15-(n))) #define RBIT(b,n) (1<<(8*sizeof(n)-1-(b))) /* * Bit encodings for Machine State Register (MSR) */ #define MSG_SF BIT(0) /* 64 mode */ #define MSR_HV BIT(3) /* Hypervisor State */ #define MSR_VEC BIT(38) /* Vector Enable */ #define MSR_VSX BIT(40) /* VSX enable */ #define MSR_SEC BIT(41) /* Secure mode enable */ #define MSR_EE BIT(48) /* External Interrupt enable */ #define MSR_PR BIT(49) /* Supervisor/User privilege */ #define MSR_FP BIT(50) /* Floating Point enable */ #define MSR_ME BIT(51) /* Machine Check enable */ #define MSR_FE0 BIT(52) /* Floating Exception mode 0 */ #define MSR_SE BIT(53) /* Single Step (optional) */ #define MSR_BE BIT(54) /* Branch Trace (optional) */ #define MSR_FE1 BIT(55) /* Floating Exception mode 1 */ #define MSR_IR BIT(58) /* Instruction MMU enable */ #define MSR_DR BIT(59) /* Data MMU enable */ #define MSR_PM BIT(61) /* Performance Monitor marked mode (604e specific) */ #define MSR_RI BIT(62) /* Recoverable Exception */ #define MSR_LE BIT(63) /* Little-Endian enable */ /* SRR1 bits for TLB operations */ #define MSR_SR0 0xf0000000 /* Saved bits from CR register */ #define MSR_KEY BIT(12) /* Copy of Ks or Kp bit */ #define MSR_IMISS BIT(13) /* It was an I miss */ #define MSR_WAY BIT(14) /* TLB set to be replaced */ #define MSR_STORE BIT(15) /* Miss caused by a store */