ref: c85bc69f741a003f6ebccdae4168a8527c775823
parent: 982b9ee2e2f44065a4e05fb2d485acc172b845f0
author: Naveen Narayanan zerous <zerous@nocebo.space>
date: Thu May 24 07:35:39 EDT 2018
Add ADDW to x86.dat Update ins.c to include 16 bit registers. Update ins.c to include reg16toint(). Update ins.c to include reg16_reg16(). Update proc.h to include AREG_16CLASS. Name enum 'class'.
--- a/as/target/x86/ins.c
+++ b/as/target/x86/ins.c
@@ -32,6 +32,16 @@
case AREG_DH:
return R8CLASS;
+ case AREG_AX:
+ case AREG_BX:
+ case AREG_CX:
+ case AREG_DX:
+ case AREG_DI:
+ case AREG_SI:
+ case AREG_SP:
+ case AREG_BP:
+ return R16CLASS;
+
case AREG_CS:
case AREG_DS:
case AREG_SS:
@@ -58,37 +68,29 @@
case AREG_VIP:
case AREG_ID:
- case AREG_AX:
case AREG_EAX:
case AREG_RAX:
- case AREG_BX:
case AREG_EBX:
case AREG_RBX:
- case AREG_CX:
case AREG_ECX:
case AREG_RCX:
- case AREG_DX:
case AREG_EDX:
case AREG_RDX:
- case AREG_SI:
case AREG_SIL:
case AREG_ESI:
case AREG_RSI:
- case AREG_DI:
case AREG_DIL:
case AREG_EDI:
case AREG_RDI:
- case AREG_SP:
case AREG_SPL:
case AREG_ESP:
case AREG_RSP:
- case AREG_BP:
case AREG_BPL:
case AREG_EBP:
case AREG_RBP:
@@ -202,6 +204,9 @@
break;
case AREG_R8CLASS:
class = R8CLASS;
+ goto check_class;
+ case AREG_R16CLASS:
+ class = R16CLASS;
check_class:
if ((getclass(np) & class) == 0)
return 0;
@@ -261,6 +266,35 @@
src = reg8toint(args[0]);
dst = reg8toint(args[1]);
+ buf[0] = op->bytes[0];
+ buf[1] = addrbyte(REG_MODE, src, dst);
+ emit(buf, 2);
+}
+
+static int
+reg16toint(Node *np)
+{+ switch (np->sym->value) {+ case AREG_AX: return 0;
+ case AREG_CX: return 1;
+ case AREG_DX: return 2;
+ case AREG_BX: return 3;
+ case AREG_SP: return 4;
+ case AREG_BP: return 5;
+ case AREG_SI: return 6;
+ case AREG_DI: return 7;
+ default: abort();
+ }
+}
+
+void
+reg16_reg16(Op *op, Node **args)
+{+ int src, dst;
+ char buf[2];
+
+ src = reg16toint(args[0]);
+ dst = reg16toint(args[1]);
buf[0] = op->bytes[0];
buf[1] = addrbyte(REG_MODE, src, dst);
emit(buf, 2);
--- a/as/target/x86/proc.h
+++ b/as/target/x86/proc.h
@@ -148,8 +148,10 @@
AREG_MXCSR,
AREG_R8CLASS, /* register class for 8 bit registers in i286 */
+ AREG_R16CLASS, /* register class for 16 bit registers in i286 */
};
-enum {- R8CLASS = 1 << 0,
+enum class {+ R8CLASS = 1 << 0,
+ R16CLASS = 1 << 1,
};
--- a/as/target/x86/x86.dat
+++ b/as/target/x86/x86.dat
@@ -25,3 +25,4 @@
# 8 bit arithmetic operations
ADDB reg8,reg8 2 0x00 reg8_reg8 I286,I386,AMD64
+ADDW reg16,reg16 2 0x01 reg16_reg16 I286,I386,AMD64