ref: 8b6a2d7d21c67db8b1fbc4eaabf3496bcc07941d
parent: 2b760d39218681e0bd7ff9a73d008b4072c091c3
author: Roberto E. Vargas Caballero <k0ga@shike2.com>
date: Sun Dec 17 14:50:23 EST 2017
[as-z80] Add index load operations
--- a/as/target/gen.awk
+++ b/as/target/gen.awk
@@ -74,7 +74,11 @@
} else if (match(a, /^imm32/)) {out = out "AIMM32"
} else if (match(a, /^imm64/)) {- out = "AIMM64"
+ out = out "AIMM64"
+ } else if (match(a, /^idx_IY/)) {+ out = out "AINDEX_IY"
+ } else if (match(a, /^idx_IX/)) {+ out = out "AINDEX_IX"
} else if (match(a, /^reg_dd/)) {out = out "AREG_DDCLASS"
} else if (match(a, /^reg_qq/)) {--- a/as/target/x80/ins.c
+++ b/as/target/x80/ins.c
@@ -129,6 +129,29 @@
}
void
+r8_idx(Op *op, Node **args)
+{+ args[1] = args[1]->left;
+ r8_imm8(op, args);
+}
+
+void
+idx_r8(Op *op, Node **args)
+{+ Node *par1, *par2;
+ unsigned char buf[3];
+ int n = op->size;
+
+ par1 = args[0]->left;
+ par2 = args[1];
+
+ memcpy(buf, op->bytes, n-1);
+ buf[n-1] = par1->sym->value;
+ buf[n-2] |= reg2int(par2->sym->argtype);
+ emit(buf, n);
+}
+
+void
imm8(Op *op, Node **args)
{Node *par1, *par2;
--- a/as/target/x80/proc.h
+++ b/as/target/x80/proc.h
@@ -35,6 +35,9 @@
AREG_DDCLASS, /* register class for BC, DE, HL and SP */
AREG_QQCLASS, /* register class for BC, DE, HL and AF */
+ AINDEX_IX,
+ AINDEX_IY,
+
AINDER_HL, /* (HL) */
};
--- a/as/target/x80/x80.dat
+++ b/as/target/x80/x80.dat
@@ -77,6 +77,7 @@
# dd is any register from BC, DE, HL, SP
# qq is any register from BC, DE, HL, AF
+# 8 bit load group
LD reg_r,imm8 2 0x06 r8_imm8 Z80,R800,GB80
LD reg_p,imm8 3 0xdd,0x06 r8_imm8 Z80,R800
LD reg_q,imm8 3 0xfd,0x06 r8_imm8 Z80,R800
@@ -87,6 +88,11 @@
LD reg_q,reg_q 2 0xfd,0x40 r8_r8 Z80,R800
LD indir_HL,reg_r 1 0x70 xx_r8 Z80,R800,GB80
LD reg_r,indir_HL 1 0x46 r8_xx Z80,R800,GB80
+
+LD reg_r,idx_IX 3 0xdd,0x46 r8_idx Z80,R800
+LD reg_r,idx_IY 3 0xfd,0x46 r8_idx Z80,R800
+LD idx_IX,reg_r 3 0xdd,0x70 idx_r8 Z80,R800
+LD idx_IY,reg_r 3 0xfd,0x70 idx_r8 Z80,R800
# 16 bit load group
LD reg_dd,imm16 3 0x01 r16_imm16 Z80,R800,GB80
--- a/as/target/z80/proc.c
+++ b/as/target/z80/proc.c
@@ -104,6 +104,17 @@
if (!(*class)(np->sym->argtype))
return 0;
break;
+ case AINDEX_IY:
+ arg = AREG_IY;
+ goto index_address;
+ case AINDEX_IX:
+ arg = AREG_IX;
+ index_address:
+ if (np->addr != AINDEX)
+ return 0;
+ if (np->left->left->sym->argtype != arg)
+ return 0;
+ break;
case AIMM8:
case AIMM16:
case AIMM32: