ref: 3cd935a51ca42e36e652f5519a2450c34004560a
parent: a50b052c5182c502499380acc3ebaa2cd4aaacbb
author: Roberto E. Vargas Caballero <k0ga@shike2.com>
date: Sun Dec 17 15:13:32 EST 2017
[as-z80] Add indirect BC and DE load instructions
--- a/as/target/gen.awk
+++ b/as/target/gen.awk
@@ -91,6 +91,10 @@
out = out "AREG_RCLASS"
} else if (match(a, /^regA/)) {out = out "AREG_A"
+ } else if (match(a, /^indir_DE/)) {+ out = out "AINDER_DE"
+ } else if (match(a, /^indir_BC/)) {+ out = out "AINDER_BC"
} else if (match(a, /^indir_HL/)) {out = out "AINDER_HL"
} else if (match(a, /^regSP/)) {--- a/as/target/x80/proc.h
+++ b/as/target/x80/proc.h
@@ -35,10 +35,12 @@
AREG_DDCLASS, /* register class for BC, DE, HL and SP */
AREG_QQCLASS, /* register class for BC, DE, HL and AF */
- AINDEX_IX,
- AINDEX_IY,
+ AINDEX_IX, /* (IX+d) */
+ AINDEX_IY, /* (IX+d) */
AINDER_HL, /* (HL) */
+ AINDER_DE, /* (DE) */
+ AINDER_BC, /* (BC) */
};
extern int rclass(int reg);
--- a/as/target/x80/x80.dat
+++ b/as/target/x80/x80.dat
@@ -98,6 +98,15 @@
LD idx_IX,imm8 3 0xdd,0x36 idx_imm8 Z80,R800
LD idx_IY,imm8 3 0xfd,0x36 idx_imm8 Z80,R800
+LD regA,indir_BC 1 0x0a noargs Z80,R800,GB80
+LD regA,indir_DE 1 0x1a noargs Z80,R800,GB80
+LD regA,dir 3 0x3a dir Z80,R800,GB80
+
+LD indir_BC,regA 1 0x2 noargs Z80,R800,GB80
+LD indir_DE,regA 1 0x12 noargs Z80,R800,GB80
+LD dir,regA 3 0x32 dir Z80,R800,GB80
+
+
# 16 bit load group
LD reg_dd,imm16 3 0x01 r16_imm16 Z80,R800,GB80
LD regIX,imm16 4 0xdd,0x21 imm16 Z80,R800