ref: ecc5998bcf59044688d92c89d73e8b5247c02955
parent: 0ffbb36ddc5a1be8ee38ab3bdc663fd5ea99da78
author: Kaustubh Raste <kaustubh.raste@imgtec.com>
date: Tue Nov 22 12:49:17 EST 2016
Fix mips dspr2 build warning Change-Id: Ia8fb3ed124f01384e7896e309c9ff22c05b40719
--- a/vp8/common/mips/dspr2/filter_dspr2.c
+++ b/vp8/common/mips/dspr2/filter_dspr2.c
@@ -1469,6 +1469,7 @@
unsigned char src_ptr_r2;
unsigned char src_ptr_r3;
unsigned char *cm = ff_cropTbl + CROP_WIDTH;
+ (void)output_width;
vector4a = 64;
--- a/vp8/common/mips/dspr2/vp8_loopfilter_filters_dspr2.c
+++ b/vp8/common/mips/dspr2/vp8_loopfilter_filters_dspr2.c
@@ -306,6 +306,7 @@
uint32_t hev;
uint32_t pm1, p0, p1, p2, p3, p4, p5, p6;
unsigned char *sm1, *s0, *s1, *s2, *s3, *s4, *s5, *s6;
+ (void)count;
mask = 0;
hev = 0;
@@ -498,6 +499,7 @@
uint32_t hev;
uint32_t pm1, p0, p1, p2, p3, p4, p5, p6;
unsigned char *sm1, *s0, *s1, *s2, *s3, *s4, *s5, *s6;
+ (void)count;
mask = 0;
hev = 0;
@@ -918,6 +920,7 @@
uint32_t pm1, p0, p1, p2, p3, p4, p5, p6;
unsigned char *s1, *s2, *s3, *s4;
uint32_t prim1, prim2, sec3, sec4, prim3, prim4;
+ (void)count;
/* loop filter designed to work using chars so that we can make maximum use
* of 8 bit simd instructions.
@@ -1612,6 +1615,7 @@
uint32_t mask, hev;
uint32_t pm1, p0, p1, p2, p3, p4, p5, p6;
unsigned char *sm1, *s0, *s1, *s2, *s3, *s4, *s5, *s6;
+ (void)count;
mask = 0;
hev = 0;
@@ -1915,6 +1919,7 @@
uint32_t pm1, p0, p1, p2, p3, p4, p5, p6;
unsigned char *s1, *s2, *s3, *s4;
uint32_t prim1, prim2, sec3, sec4, prim3, prim4;
+ (void)count;
mask = 0;
hev = 0;
--- a/vpx_dsp/mips/convolve8_avg_dspr2.c
+++ b/vpx_dsp/mips/convolve8_avg_dspr2.c
@@ -403,8 +403,11 @@
const int16_t *filter_y, int filter_y_stride, int w,
int h) {
int x, y;
- uint32_t tp1, tp2, tn1;
- uint32_t tp3, tp4, tn2;
+ uint32_t tp1, tp2, tn1, tp3, tp4, tn2;
+ (void)filter_x;
+ (void)filter_x_stride;
+ (void)filter_y;
+ (void)filter_y_stride;
/* prefetch data to cache memory */
prefetch_load(src);
--- a/vpx_dsp/mips/convolve8_dspr2.c
+++ b/vpx_dsp/mips/convolve8_dspr2.c
@@ -1307,6 +1307,7 @@
assert(y_step_q4 == 16);
assert(((const int32_t *)filter_x)[1] != 0x800000);
assert(((const int32_t *)filter_y)[1] != 0x800000);
+ (void)x_step_q4;
/* bit positon for extract from acc */
__asm__ __volatile__("wrdsp %[pos], 1 \n\t"
@@ -1398,6 +1399,10 @@
const int16_t *filter_y, int filter_y_stride,
int w, int h) {
int x, y;
+ (void)filter_x;
+ (void)filter_x_stride;
+ (void)filter_y;
+ (void)filter_y_stride;
/* prefetch data to cache memory */
prefetch_load(src);
--- a/vpx_dsp/mips/intrapred16_dspr2.c
+++ b/vpx_dsp/mips/intrapred16_dspr2.c
@@ -15,6 +15,7 @@
const uint8_t *above, const uint8_t *left) {
int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8;
int32_t tmp9, tmp10, tmp11, tmp12, tmp13, tmp14, tmp15, tmp16;
+ (void)above;
__asm__ __volatile__(
"lb %[tmp1], (%[left]) \n\t"
--- a/vpx_dsp/mips/intrapred4_dspr2.c
+++ b/vpx_dsp/mips/intrapred4_dspr2.c
@@ -14,6 +14,7 @@
void vpx_h_predictor_4x4_dspr2(uint8_t *dst, ptrdiff_t stride,
const uint8_t *above, const uint8_t *left) {
int32_t tmp1, tmp2, tmp3, tmp4;
+ (void)above;
__asm__ __volatile__(
"lb %[tmp1], (%[left]) \n\t"
--- a/vpx_dsp/mips/intrapred8_dspr2.c
+++ b/vpx_dsp/mips/intrapred8_dspr2.c
@@ -14,6 +14,7 @@
void vpx_h_predictor_8x8_dspr2(uint8_t *dst, ptrdiff_t stride,
const uint8_t *above, const uint8_t *left) {
int32_t tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8;
+ (void)above;
__asm__ __volatile__(
"lb %[tmp1], (%[left]) \n\t"