ref: 6377f9d966af2722d28663038a69c20e2c331da5
parent: c7e2bd62987ba5e4f8c74feed9175e07bb99ff22
author: Kaustubh Raste <kaustubh.raste@imgtec.com>
date: Mon Jan 9 12:30:16 EST 2017
Add mips dspr2 partial idct tests Change-Id: Idf4003ea6f9a2a42a9f26e156bee73697acb7a37
--- a/test/partial_idct_test.cc
+++ b/test/partial_idct_test.cc
@@ -624,6 +624,38 @@
::testing::ValuesIn(ssse3_partial_idct_tests));
#endif // HAVE_SSSE3 && ARCH_X86_64 && !CONFIG_EMULATE_HARDWARE
+#if HAVE_DSPR2 && !CONFIG_EMULATE_HARDWARE && !CONFIG_VP9_HIGHBITDEPTH
+const PartialInvTxfmParam dspr2_partial_idct_tests[] = {+ make_tuple(&vpx_fdct32x32_c, &wrapper<vpx_idct32x32_1024_add_c>,
+ &wrapper<vpx_idct32x32_1024_add_dspr2>, TX_32X32, 1024, 8, 1),
+ make_tuple(&vpx_fdct32x32_c, &wrapper<vpx_idct32x32_1024_add_c>,
+ &wrapper<vpx_idct32x32_1024_add_dspr2>, TX_32X32, 135, 8, 1),
+ make_tuple(&vpx_fdct32x32_c, &wrapper<vpx_idct32x32_1024_add_c>,
+ &wrapper<vpx_idct32x32_34_add_dspr2>, TX_32X32, 34, 8, 1),
+ make_tuple(&vpx_fdct32x32_c, &wrapper<vpx_idct32x32_1024_add_c>,
+ &wrapper<vpx_idct32x32_1_add_dspr2>, TX_32X32, 1, 8, 1),
+ make_tuple(&vpx_fdct16x16_c, &wrapper<vpx_idct16x16_256_add_c>,
+ &wrapper<vpx_idct16x16_256_add_dspr2>, TX_16X16, 256, 8, 1),
+ make_tuple(&vpx_fdct16x16_c, &wrapper<vpx_idct16x16_256_add_c>,
+ &wrapper<vpx_idct16x16_10_add_dspr2>, TX_16X16, 10, 8, 1),
+ make_tuple(&vpx_fdct16x16_c, &wrapper<vpx_idct16x16_256_add_c>,
+ &wrapper<vpx_idct16x16_1_add_dspr2>, TX_16X16, 1, 8, 1),
+ make_tuple(&vpx_fdct8x8_c, &wrapper<vpx_idct8x8_64_add_c>,
+ &wrapper<vpx_idct8x8_64_add_dspr2>, TX_8X8, 64, 8, 1),
+ make_tuple(&vpx_fdct8x8_c, &wrapper<vpx_idct8x8_64_add_c>,
+ &wrapper<vpx_idct8x8_12_add_dspr2>, TX_8X8, 12, 8, 1),
+ make_tuple(&vpx_fdct8x8_c, &wrapper<vpx_idct8x8_64_add_c>,
+ &wrapper<vpx_idct8x8_1_add_dspr2>, TX_8X8, 1, 8, 1),
+ make_tuple(&vpx_fdct4x4_c, &wrapper<vpx_idct4x4_16_add_c>,
+ &wrapper<vpx_idct4x4_16_add_dspr2>, TX_4X4, 16, 8, 1),
+ make_tuple(&vpx_fdct4x4_c, &wrapper<vpx_idct4x4_16_add_c>,
+ &wrapper<vpx_idct4x4_1_add_dspr2>, TX_4X4, 1, 8, 1)
+};
+
+INSTANTIATE_TEST_CASE_P(DSPR2, PartialIDctTest,
+ ::testing::ValuesIn(dspr2_partial_idct_tests));
+#endif // HAVE_DSPR2 && !CONFIG_EMULATE_HARDWARE && !CONFIG_VP9_HIGHBITDEPTH
+
#if HAVE_MSA && !CONFIG_EMULATE_HARDWARE && !CONFIG_VP9_HIGHBITDEPTH
// 32x32_135_ is implemented using the 1024 version.
const PartialInvTxfmParam msa_partial_idct_tests[] = {