ref: 7760836ddbcc9250ccb717d13918a37e3722604a
parent: 96ecd420fa40b629e6200c7fcbd85d00ad83e139
author: Sigrid Solveig Haflínudóttir <sigrid@ftrv.se>
date: Sun Apr 30 17:16:59 EDT 2023
more random stuff
--- a/g1regs.h
+++ b/g1regs.h
@@ -16,7 +16,7 @@
SW_DEC_STRENDIAN_E = 21, /* = 1 (little endian) */
SW_DEC_INSWAP32_E = 20, /* = 1 (64-bit) */
SW_DEC_OUTSWAP32_E = 19, /* = 1 (64-bit) */
- SW_DEC_CLK_GATE_E = 10, /* clock gate (0=gated 1=running) */
+ SW_DEC_CLK_GATE_E = 10, /* clock gate (1 = gated between each picture) */
SW_DEC_IN_ENDIAN = 9, /* = 1 (little endian) */
SW_DEC_OUT_ENDIAN = 8, /* = 1 (little endian) */
SW_DEC_MAX_BURST = 0, /* = 16 for AIX is the max */
@@ -39,7 +39,7 @@
/* SWREG5 */
SW_STRM_START_BIT = 26, /* = 0 (always starting at byte boundary) */
- SW_TYPE1_QUANT_E = 24, /* = pps.pic_scaling_matrix_present_flag */
+ SW_SCALING_LIST_E = 24, /* = pps.pic_scaling_matrix_present_flag */
SW_CH_QP_OFFSET = 19, /* = pps.chroma_qp_index_offset */
SW_CH_QP_OFFSET2 = 14, /* = pps.second_chroma_qp_index_offset */
SW_FIELDPIC_FLAG_E = 0, /* = !sps.frame_mbs_only_flag */
--- a/hantest.c
+++ b/hantest.c
@@ -1,6 +1,5 @@
#include <u.h>
#include <libc.h>
-#include <ctype.h>
#include "g1regs.h"
enum {@@ -12,6 +11,37 @@
typedef struct VPUctx VPUctx;
+#define Default_4x4_Intra {6, 13, 13, 20, 20, 20, 28, 28, 28, 28, 32, 32, 32, 37, 37, 42}+#define Default_4x4_Inter {10, 14, 14, 20, 20, 20, 24, 24, 24, 24, 27, 27, 27, 30, 30, 34}+#define Default_8x8_Intra \
+ {6, 10, 10, 13, 11, 13, 16, 16, 16, 16, 18, 18, 18, 18, 18, 23, \+ 23, 23, 23, 23, 23, 25, 25, 25, 25, 25, 25, 25, 27, 27, 27, 27, \
+ 27, 27, 27, 27, 29, 29, 29, 29, 29, 29, 29, 31, 31, 31, 31, 31, \
+ 31, 33, 33, 33, 33, 33, 36, 36, 36, 36, 38, 38, 38, 40, 40, 42}
+#define Default_8x8_Inter \
+ {9, 13, 13, 15, 13, 15, 17, 17, 17, 17, 19, 19, 19, 19, 19, 21, \+ 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 24, 24, 24, 24, \
+ 24, 24, 24, 24, 25, 25, 25, 25, 25, 25, 25, 27, 27, 27, 27, 27, \
+ 27, 28, 28, 28, 28, 28, 30, 30, 30, 30, 32, 32, 32, 33, 33, 35}
+
+static u8int defsl4x4[6][16] = {+ Default_4x4_Intra, /* Sl_4x4_Intra_Y */
+ Default_4x4_Intra, /* Sl_4x4_Intra_Cb */
+ Default_4x4_Intra, /* Sl_4x4_Intra_Cr */
+ Default_4x4_Inter, /* Sl_4x4_Inter_Y */
+ Default_4x4_Inter, /* Sl_4x4_Inter_Cb */
+ Default_4x4_Inter, /* Sl_4x4_Inter_Cr */
+};
+
+static u8int defs8x8[6][64] = {+ Default_8x8_Intra, /* Sl_8x8_Intra_Y */
+ Default_8x8_Inter, /* Sl_8x8_Inter_Y */
+ Default_8x8_Intra, /* Sl_8x8_Intra_Cb */
+ Default_8x8_Inter, /* Sl_8x8_Inter_Cb */
+ Default_8x8_Intra, /* Sl_8x8_Intra_Cr */
+ Default_8x8_Inter, /* Sl_8x8_Inter_Cr */
+};
+
struct VPUctx {int process;
int slen;
@@ -89,7 +119,7 @@
c->sps.max_num_ref_frames << SW_REF_FRAMES;
g1[5] = 0 << SW_STRM_START_BIT |
- c->pps.pic_scaling_matrix_present_flag << SW_TYPE1_QUANT_E |
+ c->pps.pic_scaling_matrix_present_flag << SW_SCALING_LIST_E |
(c->pps.chroma_qp_index_offset & ((1<<5)-1)) << SW_CH_QP_OFFSET |
(c->pps.second_chroma_qp_index_offset & ((1<<5)-1)) << SW_CH_QP_OFFSET2 |
(c->sps.frame_mbs_only_flag == 0) << SW_FIELDPIC_FLAG_E;