ref: 08088411259056f63774befb2d00951fdd5c46ba
parent: 71fb707875b95672f0cd1cb153c890eff4219720
author: Timothy B. Terriberry <territim@amazon.com>
date: Wed Jul 6 11:23:12 EDT 2022
Only build platform RTCD sources when enabled. To avoid issues with empty compilation units.
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -381,6 +381,8 @@
message(ERROR "Runtime cpu capability detection is enabled while CPU_INFO is not supported")
endif()
endif()
+ add_sources_group(opus celt ${celt_sources_x86_rtcd})+ add_sources_group(opus silk ${silk_sources_x86_rtcd})endif()
if(SSE1_SUPPORTED)
@@ -465,15 +467,13 @@
endif()
endif()
- if(CMAKE_SYSTEM_PROCESSOR MATCHES "(arm|aarch64)")
- add_sources_group(opus celt ${celt_sources_arm})- endif()
-
if(COMPILER_SUPPORT_NEON)
if(OPUS_MAY_HAVE_NEON)
if(RUNTIME_CPU_CAPABILITY_DETECTION)
message(STATUS "OPUS_MAY_HAVE_NEON enabling runtime detection")
target_compile_definitions(opus PRIVATE OPUS_HAVE_RTCD)
+ add_sources_group(opus celt ${celt_sources_arm_rtcd})+ add_sources_group(opus silk ${silk_sources_arm_rtcd})else()
message(ERROR "Runtime cpu capability detection needed for MAY_HAVE_NEON")
endif()
--- a/Makefile.am
+++ b/Makefile.am
@@ -36,6 +36,11 @@
OPUS_SOURCES += $(OPUS_SOURCES_FLOAT)
endif
+if CPU_X86
+if HAVE_RTCD
+CELT_SOURCES += $(CELT_SOURCES_X86_RTCD)
+SILK_SOURCES += $(SILK_SOURCES_X86_RTCD)
+endif
if HAVE_SSE
CELT_SOURCES += $(CELT_SOURCES_SSE)
endif
@@ -45,10 +50,13 @@
if HAVE_SSE4_1
CELT_SOURCES += $(CELT_SOURCES_SSE4_1)
endif
+endif
if CPU_ARM
-CELT_SOURCES += $(CELT_SOURCES_ARM)
-SILK_SOURCES += $(SILK_SOURCES_ARM)
+if HAVE_RTCD
+CELT_SOURCES += $(CELT_SOURCES_ARM_RTCD)
+SILK_SOURCES += $(SILK_SOURCES_ARM_RTCD)
+endif
if HAVE_ARM_NEON_INTR
CELT_SOURCES += $(CELT_SOURCES_ARM_NEON_INTR)
--- a/celt/meson.build
+++ b/celt/meson.build
@@ -10,6 +10,10 @@
celt_static_libs = []
+if host_cpu_family in ['x86', 'x86_64'] and opus_conf.has('OPUS_HAVE_RTCD')+ celt_sources += sources['CELT_SOURCES_X86_RTCD']
+endif
+
foreach intr_name : ['sse', 'sse2', 'sse4_1', 'neon_intr']
have_intr = get_variable('have_' + intr_name)if not have_intr
@@ -30,7 +34,9 @@
endif
if host_cpu_family in ['arm', 'aarch64'] and have_arm_intrinsics_or_asm
- celt_sources += sources['CELT_SOURCES_ARM']
+ if opus_conf.has('OPUS_HAVE_RTCD')+ celt_sources += sources['CELT_SOURCES_ARM_RTCD']
+ endif
if have_arm_ne10
celt_sources += sources['CELT_SOURCES_ARM_NE10']
endif
--- a/celt_sources.mk
+++ b/celt_sources.mk
@@ -18,9 +18,11 @@
celt/rate.c \
celt/vq.c
-CELT_SOURCES_SSE = \
+CELT_SOURCES_X86_RTCD = \
celt/x86/x86cpu.c \
-celt/x86/x86_celt_map.c \
+celt/x86/x86_celt_map.c
+
+CELT_SOURCES_SSE = \
celt/x86/pitch_sse.c
CELT_SOURCES_SSE2 = \
@@ -31,7 +33,7 @@
celt/x86/celt_lpc_sse4_1.c \
celt/x86/pitch_sse4_1.c
-CELT_SOURCES_ARM = \
+CELT_SOURCES_ARM_RTCD = \
celt/arm/armcpu.c \
celt/arm/arm_celt_map.c
--- a/cmake/OpusSources.cmake
+++ b/cmake/OpusSources.cmake
@@ -9,9 +9,11 @@
get_opus_sources(SILK_SOURCES silk_sources.mk silk_sources)
get_opus_sources(SILK_SOURCES_FLOAT silk_sources.mk silk_sources_float)
get_opus_sources(SILK_SOURCES_FIXED silk_sources.mk silk_sources_fixed)
+get_opus_sources(SILK_SOURCES_X86_RTCD silk_sources.mk silk_sources_x86_rtcd)
get_opus_sources(SILK_SOURCES_SSE4_1 silk_sources.mk silk_sources_sse4_1)
get_opus_sources(SILK_SOURCES_FIXED_SSE4_1 silk_sources.mk
silk_sources_fixed_sse4_1)
+get_opus_sources(SILK_SOURCES_ARM_RTCD silk_sources.mk silk_sources_arm_rtcd)
get_opus_sources(SILK_SOURCES_ARM_NEON_INTR silk_sources.mk
silk_sources_arm_neon_intr)
get_opus_sources(SILK_SOURCES_FIXED_ARM_NEON_INTR silk_sources.mk
@@ -23,10 +25,11 @@
get_opus_sources(CELT_HEAD celt_headers.mk celt_headers)
get_opus_sources(CELT_SOURCES celt_sources.mk celt_sources)
+get_opus_sources(CELT_SOURCES_X86_RTCD celt_sources.mk celt_sources_x86_rtcd)
get_opus_sources(CELT_SOURCES_SSE celt_sources.mk celt_sources_sse)
get_opus_sources(CELT_SOURCES_SSE2 celt_sources.mk celt_sources_sse2)
get_opus_sources(CELT_SOURCES_SSE4_1 celt_sources.mk celt_sources_sse4_1)
-get_opus_sources(CELT_SOURCES_ARM celt_sources.mk celt_sources_arm)
+get_opus_sources(CELT_SOURCES_ARM_RTCD celt_sources.mk celt_sources_arm_rtcd)
get_opus_sources(CELT_SOURCES_ARM_ASM celt_sources.mk celt_sources_arm_asm)
get_opus_sources(CELT_AM_SOURCES_ARM_ASM celt_sources.mk
celt_am_sources_arm_asm)
--- a/configure.ac
+++ b/configure.ac
@@ -195,6 +195,7 @@
rtcd_support=no
cpu_arm=no
+cpu_x86=no
AS_IF([test x"${enable_asm}" = x"yes"],[inline_optimization="No inline ASM for your platform, please send patches"
@@ -535,6 +536,7 @@
],
[i?86|x86_64],
[
+ cpu_x86=yes
OPUS_CHECK_INTRINSICS(
[SSE],
[$X86_SSE_CFLAGS],
@@ -744,6 +746,7 @@
[test x"$OPUS_ARM_MAY_HAVE_NEON_INTR" = x"1"])
AM_CONDITIONAL([HAVE_ARM_NE10],
[test x"$HAVE_ARM_NE10" = x"1"])
+AM_CONDITIONAL([CPU_X86], [test "$cpu_x86" = "yes"])
AM_CONDITIONAL([HAVE_SSE],
[test x"$OPUS_X86_MAY_HAVE_SSE" = x"1"])
AM_CONDITIONAL([HAVE_SSE2],
@@ -753,6 +756,8 @@
AM_CONDITIONAL([HAVE_AVX],
[test x"$OPUS_X86_MAY_HAVE_AVX" = x"1"])
+AM_CONDITIONAL([HAVE_RTCD],
+ [test x"$enable_rtcd" = x"yes" -a x"$rtcd_support" != x"no"])
AS_IF([test x"$enable_rtcd" = x"yes"],[
AS_IF([test x"$rtcd_support" != x"no"],[
AC_DEFINE([OPUS_HAVE_RTCD], [1],
--- a/silk/meson.build
+++ b/silk/meson.build
@@ -21,6 +21,16 @@
silk_includes = [opus_includes, include_directories('float', 'fixed')]silk_static_libs = []
+if host_cpu_family in ['x86', 'x86_64'] and opus_conf.has('OPUS_HAVE_RTCD')+ silk_sources += sources['SILK_SOURCES_X86_RTCD']
+endif
+
+if host_cpu_family in ['arm', 'aarch64'] and have_arm_intrinsics_or_asm
+ if opus_conf.has('OPUS_HAVE_RTCD')+ silk_sources += sources['SILK_SOURCES_ARM_RTCD']
+ endif
+endif
+
foreach intr_name : ['sse4_1', 'neon_intr']
have_intr = get_variable('have_' + intr_name)if not have_intr
--- a/silk_sources.mk
+++ b/silk_sources.mk
@@ -77,15 +77,19 @@
silk/stereo_quant_pred.c \
silk/LPC_fit.c
-SILK_SOURCES_SSE4_1 = \
+SILK_SOURCES_X86_RTCD = \
+silk/x86/x86_silk_map.c
+
+SILK_SOURCES_SSE4_1 = \
silk/x86/NSQ_sse4_1.c \
silk/x86/NSQ_del_dec_sse4_1.c \
-silk/x86/x86_silk_map.c \
silk/x86/VAD_sse4_1.c \
silk/x86/VQ_WMat_EC_sse4_1.c
+SILK_SOURCES_ARM_RTCD = \
+silk/arm/arm_silk_map.c
+
SILK_SOURCES_ARM_NEON_INTR = \
-silk/arm/arm_silk_map.c \
silk/arm/biquad_alt_neon_intr.c \
silk/arm/LPC_inv_pred_gain_neon_intr.c \
silk/arm/NSQ_del_dec_neon_intr.c \