shithub: mc

Download patch

ref: 33ee7d302c1458d5e36a7d6bde5e7666cb394769
parent: 1ad37cb101e06f5daf7f8ac450f17fdd2454eeba
author: Ori Bernstein <orib@google.com>
date: Mon Jul 30 14:45:25 EDT 2012 

Add 64 bit registers to x86 defs.

    We're gonna be supporting x64.


--- a/8/asm.h
+++ b/8/asm.h
@@ -40,6 +40,7 @@
     ModeB, /* byte */
     ModeS, /* short */
     ModeL, /* long */
+    ModeQ, /* quad */
     ModeF, /* float32 */
     ModeD, /* float64 */
     Nmode,
--- a/8/regs.def
+++ b/8/regs.def
@@ -4,6 +4,18 @@
 Reg(Rcl, "%cl", ModeB)
 Reg(Rdl, "%dl", ModeB)
 Reg(Rbl, "%bl", ModeB)
+Reg(Rsil, "%sil", ModeB)
+Reg(Rdil, "%dil", ModeB)
+Reg(Rspl, "%spl", ModeB)
+Reg(Rbpl, "%bpl", ModeB)
+Reg(R8b, "%r8b", ModeB)
+Reg(R9b, "%r9b", ModeB)
+Reg(R10b, "%r10b", ModeB)
+Reg(R11b, "%r11b", ModeB)
+Reg(R12b, "%r12b", ModeB)
+Reg(R13b, "%r13b", ModeB)
+Reg(R14b, "%r14b", ModeB)
+Reg(R15b, "%r15b", ModeB)
 
 /* high byte regs. We *NEVER* allocate these */
 Reg(Rah, "%ah", ModeB)
@@ -18,7 +30,18 @@
 Reg(Rdx, "%dx", ModeS)
 Reg(Rsi, "%si", ModeS)
 Reg(Rdi, "%di", ModeS)
+Reg(Rsp, "%sp", ModeS)
+Reg(Rbp, "%bp", ModeS)
+Reg(R8w, "%r8w", ModeS)
+Reg(R9w, "%r9w", ModeS)
+Reg(R10w, "%r10w", ModeS)
+Reg(R11w, "%r11w", ModeS)
+Reg(R12w, "%r12w", ModeS)
+Reg(R13w, "%r13w", ModeS)
+Reg(R14w, "%r14w", ModeS)
+Reg(R15w, "%r15w", ModeS)
 
+
 /* long regs */
 Reg(Reax, "%eax", ModeL)
 Reg(Recx, "%ecx", ModeL)
@@ -28,4 +51,31 @@
 Reg(Redi, "%edi", ModeL)
 Reg(Resp, "%esp", ModeL)
 Reg(Rebp, "%ebp", ModeL)
+Reg(R8d, "%r8d", ModeL)
+Reg(R9d, "%r9d", ModeL)
+Reg(R10d, "%r10d", ModeL)
+Reg(R11d, "%r11d", ModeL)
+Reg(R12d, "%r12d", ModeL)
+Reg(R13d, "%r13d", ModeL)
+Reg(R14d, "%r14d", ModeL)
+Reg(R15d, "%r15d", ModeL)
+
+/* quad regs */
+Reg(Rrax, "%rax", ModeQ)
+Reg(Rrcx, "%rcx", ModeQ)
+Reg(Rrdx, "%rdx", ModeQ)
+Reg(Rrbx, "%rbx", ModeQ)
+Reg(Rrsi, "%rsi", ModeQ)
+Reg(Rrdi, "%rdi", ModeQ)
+Reg(Rrsp, "%rsp", ModeQ)
+Reg(Rrbp, "%rbp", ModeQ)
+Reg(R8, "%r8", ModeQ)
+Reg(R9, "%r9", ModeQ)
+Reg(R10, "%r10", ModeQ)
+Reg(R11, "%r11", ModeQ)
+Reg(R12, "%r12", ModeQ)
+Reg(R13, "%r13", ModeQ)
+Reg(R14, "%r14", ModeQ)
+Reg(R15, "%r15", ModeQ)
+
 
-- 
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