ref: bbb4cf554c3a892a9245dd684b225d1ff1651da7
parent: 3510404ad5a5287148d89ee523aa1edb7ef8e257
author: Jean-Marc Valin <jmvalin@amazon.com>
date: Tue Jul 11 23:11:48 EDT 2023
Fix DRED/neural PLC for SILK stereo Don't attempt to run the neural PLC on the side channel since we only have one state.
--- a/silk/PLC.c
+++ b/silk/PLC.c
@@ -103,7 +103,7 @@
/****************************/
silk_PLC_update( psDec, psDecCtrl );
#ifdef NEURAL_PLC
- if ( psDec->sPLC.fs_kHz == 16 ) {
+ if ( lpcnet != NULL && psDec->sPLC.fs_kHz == 16 ) {
int k;
for( k = 0; k < psDec->nb_subfr; k += 2 ) {
lpcnet_plc_update( lpcnet, frame + k * psDec->subfr_length );
@@ -397,14 +397,14 @@
frame[ i ] = (opus_int16)silk_SAT16( silk_SAT16( silk_RSHIFT_ROUND( silk_SMULWW( sLPC_Q14_ptr[ MAX_LPC_ORDER + i ], prevGain_Q10[ 1 ] ), 8 ) ) );
}
#ifdef NEURAL_PLC
- if ( psDec->sPLC.fs_kHz == 16 ) {
+ if ( lpcnet != NULL && psDec->sPLC.fs_kHz == 16 ) {
for( k = 0; k < psDec->nb_subfr; k += 2 ) {
lpcnet_plc_conceal( lpcnet, frame + k * psDec->subfr_length );
}
- }
- /* We *should* be able to copy only from psDec->frame_length-MAX_LPC_ORDER, i.e. the last MAX_LPC_ORDER samples. */
- for( i = 0; i < psDec->frame_length; i++ ) {
- sLPC_Q14_ptr[ MAX_LPC_ORDER + i ] = (int)floor(.5 + frame[ i ] * (float)(1 << 24) / prevGain_Q10[ 1 ] );
+ /* We *should* be able to copy only from psDec->frame_length-MAX_LPC_ORDER, i.e. the last MAX_LPC_ORDER samples. */
+ for( i = 0; i < psDec->frame_length; i++ ) {
+ sLPC_Q14_ptr[ MAX_LPC_ORDER + i ] = (int)floor(.5 + frame[ i ] * (float)(1 << 24) / prevGain_Q10[ 1 ] );
+ }
}
#endif
--- a/silk/dec_API.c
+++ b/silk/dec_API.c
@@ -302,7 +302,7 @@
}
ret += silk_decode_frame( &channel_state[ n ], psRangeDec, &samplesOut1_tmp[ n ][ 2 ], &nSamplesOutDec, lostFlag, condCoding,
#ifdef NEURAL_PLC
- lpcnet,
+ n == 0 ? lpcnet : NULL,
#endif
arch);
} else {
--
⑨