shithub: n900

Download patch

ref: a92363b9e6af44877eb2b26f84e812e29d2d9534
parent: 1b15b212531f4aac9398406ab1abb5dd907239fa
author: mia soweli <mia@soweli.net>
date: Sat Aug 16 11:30:29 EDT 2025 

i2c: timeouts


--- a/sys/src/9/omap/i2comap.c
+++ b/sys/src/9/omap/i2comap.c
@@ -65,9 +65,21 @@
 static void
 omapi2cwaitbus(Ctlr *ctlr)
 {
-	/* FIXME: timeout here? */
-	while(csr32r(ctlr, Ris) & Ibb)
-		;
+	uint r;
+	uint rt;
+
+	rt = 1000;
+	while(rt){
+		r = csr32r(ctlr, Ris);
+		if (r & Ibb)
+			break;
+
+		microdelay(10);
+		rt--;
+	}
+
+	if (rt == 0)
+		error("timeout waiting for bus");
 }
 
 static int
@@ -79,17 +91,24 @@
 static uint
 omapi2cwait(Ctlr *ctlr)
 {
-	uint s;
+	u32int r;
+	u32int rt;
 
-	/* FIXME: timeout here? */
-	while(!(s = csr32r(ctlr, Ris))) {
-		if(!up || !islo())
-			continue;
+	r = 0;
+	rt = 1000;
+	while(rt){
+		r = csr32r(ctlr, Ris);
+		if(r != 0 && r != 0xffffffff)
+			break;
 
 		tsleep(ctlr, omapi2cwaitirq, ctlr, 5);
+		rt--;
 	}
 
-	return s;
+	if(rt == 0)
+		error("timeout waiting for irq");
+
+	return r;
 }
 
 static void
@@ -114,6 +133,8 @@
 omapi2cinit(I2Cbus *bus)
 {
 	Ctlr *ctlr;
+	u32int r;
+	u32int rt;
 
 	/* reset the ctlr */
 	ctlr = bus->ctlr;
@@ -120,9 +141,18 @@
 	csr32w(ctlr, Rsysc, SCreset);
 	csr32w(ctlr, Rcon, Cen);
 
-	/* FIXME: timeout here? */
-	while(!(csr32r(ctlr, Rsyss) & SSreset))
-		;
+	rt = 1000;
+	while(rt){
+		r = csr32r(ctlr, Rsyss);
+		if (r & SSreset)
+			break;
+
+		microdelay(10);
+		rt--;
+	}
+
+	if(rt == 0)
+		error("timeout waiting for reset");
 
 	intrenable(ctlr->irq, omapi2cintr, ctlr, 0, bus->name);
 	return 0;
-- 
⑨